/*
 * Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2023-2023. All rights reserved.
 */
#ifndef __HI309X_MEMMAP_H__
#define __HI309X_MEMMAP_H__

#define MMU_DDR_ADDR 0x93000000ULL
#define MMU_DDR_SIZE 0x01000000ULL
#define MMU_PAGE_BEGIN 0x93800000
#define MMU_PAGE_END (MMU_PAGE_BEGIN + 0x8000)

#define MMU_DRIVER_ADDR 0x08600000ULL
#define MMU_GIC_ADDR 0x24000000ULL
#define MMU_LOCALBUS_MEM_ADDR 0x30000000ULL
#define MMU_LOCALBUS_MEM_SIZE 0x2FFFFFFF

#define MMU_OPENAMP_ADDR 0x90000000ULL
#define MMU_OPENAMP_ADDR_SIZE 0x30000

#define CPU_RELEASE_ADDR_LEN (0x60)
#define CONFIG_SYS_SDRAM_BASE (MMU_PAGE_END + CPU_RELEASE_ADDR_LEN + 0x20)
#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE - CPU_RELEASE_ADDR_LEN)
#define CPU_RELEASE_GDTBL (CPU_RELEASE_ADDR + 0x8)
#define CPU_RELEASE_VBAR (CPU_RELEASE_ADDR + 0x10)
#define CPU_RELEASE_MMU_PAGE (CPU_RELEASE_ADDR + 0x18)
#define CPU_RELEASE_MMU_TCR (CPU_RELEASE_ADDR + 0x20)
#define CPU_RELEASE_BOOT_SYNC (CPU_RELEASE_ADDR + 0x28)

#define GMAC_MDIO_SYNC (CPU_RELEASE_ADDR + 0x2c) /* 0x8727ffc8 */
#define GMAC_LOCK_SYNC (CPU_RELEASE_ADDR + 0x30) /* 0x8727ffc8 */

#endif /* __HI309X_MEMMAP_H__ */